In order to streamline the periphery of the signal processing system of incremental encoder circuit and implementation without any increase in the encoder physical scribed line on the premise of improving the resolution of encoder and the subdivision accuracy, putting forward a kind of electronics subdivision scheme based on FPGA, this scheme obtaining high resolution and precision of the encoder position information, easy to make logical changes according to field condition. This scheme using FPGA to build subdivision methods required for each module, Modelsim software for simulation, DA module and oscilloscope to verify the data of the program. On the basis of the experimental results show that mechancial subdivision in the encoder, the scheme can be 120 times the signal subdivision, the incremental encoder resolution up to 3″, and can be , that is 10-5, subdivided after mechanical Angle precisely to five decimal places for the unit.